The present invention relates to memory systems for digital computers and the like, and, in particular, to the field of block-structured memory systems in which individual memory elements cannot be erased individually.
Many memory systems have a requirement for non-volatile data storage with in-system write capability. FLASH EPROM semiconductor memory devices are frequently used for such applications.
A FLASH memory device is partitioned internally into independent blocks, each of which forms a set of storage locations which are erasable in a single operation. These independent blocks are called erase blocks. An erase block, therefore, is the smallest unit which can be erased in a single erase operation.
High capacity FLASH memory circuits, for example a 16 Mbit device, incorporate a high level of integration of the control operations on the memory itself. This enables the FLASH circuit to perform a number of tasks. For example, erasure of an erase block within the FLASH circuit is normally controlled by an internal state machine which is initiated by an erase command at an external interface.
The erase operation defined by the internal state machine is used to remove all charge from the floating gate electrode within each memory cell in the erase block through the mechanism of charge tunnelling. Over-erasure of a cell may result in damage to the cell or cells involved. To avoid the possibility of cell damage due to over-erasure all of the cells in the FLASH EPROM are first pre-conditioned. Pre-conditioning is the name given to a process for writing each cell in the particular erase block that is being erased to the charged state. Once all of the cells in an erase block have been pre-conditioned then an erase pulse of typical duration 10 milliseconds is applied to all of the cells in the erase block simultaneously. Full erasure of a cell requires the application of several erase pulses to the cell. The number of erase pulses required to erase a cell varies between cells in the erase block.
After each erase pulse is applied each cell in the erase block is read in turn to check if the particular cell being read has reached the erase condition. An internal address counter controls the checking operation (the operation where each cell is checked to determine whether or not it is in the erased condition) for each cell in the erase block.
This erase verification operation is performed with certain internal voltage and current reference signals set to levels which guarantee an adequate margin for a normal read operation. These reference signals set the control voltage used to access a cell being verified and the threshold current against which the cell current is compared. Values are used which ensure that current conducted by a cell during access after erasure is sufficiently offset from the threshold value applied during a normal read operation to guarantee an adequate safety margin for normal operation.
If any location is detected in the unerased state, the verification process is halted and a further erase pulse is applied. This process continues until either all of the cells are verified as being correctly erased or until the operation exceeds some predetermined time limit.
Memory systems exist which treat erase blocks as independent regions of memory and provide defect tolerance by disregarding erase blocks containing faults. Thus, even if an erase block had only one defective cell the whole erase block would be disregarded. This arrangement is highly inefficient for FLASH memory architectures which use large erase blocks. This is because the arrangement only provides coarse-grained fault tolerance which does not make efficient use of available areas of functional memory within the circuit.
Thus the present invention provides a fault tolerant memory system comprising: an array of storage locations, where the array is erasable in blocks of storage locations and each block of storage locations is sub-divided into a plurality of groups of storage locations control information storage means for storing defect information for each group in each block, address counter means for addressing the groups in the particular erase block being erased, evaluation means for determining whether the defect information stored in the control information storage means for the particular group currently addressed by the address counter means indicates that the particular group contains one or more defective storage locations and incrementing means responsive to the evaluation means to increment the address counter when the current address in the address counter means addresses a group containing one or more defective locations.